Full Text Available
Note: Clicking the button above will open the full text document at the original institutional repository in a new window.
Design and Implementation of a Risc-V Based LoRa Module
The proliferation of the Internet of Things(IoT) in both scale and complexity, alongside advances in optimised edge and fog system architectures, is driving an increasing need for low power end nodes with greater computational capabilities. These distributed higher capacity nodes allow IoT infrastru...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
Department of Electrical Engineering
2024
|
| Subjects: | |
| Tags: |
No Tags, Be the first to tag this record!
|
| _version_ | 1867613292631949312 |
|---|---|
| access_status_str | Open Access |
| author | Njoroge, Mark |
| author2 | Winberg, Simon |
| author_browse | Njoroge, Mark Winberg, Simon |
| author_facet | Winberg, Simon Njoroge, Mark |
| author_sort | Njoroge, Mark |
| collection | Thesis |
| description | The proliferation of the Internet of Things(IoT) in both scale and complexity, alongside advances in optimised edge and fog system architectures, is driving an increasing need for low power end nodes with greater computational capabilities. These distributed higher capacity nodes allow IoT infrastructures to minimise the power cost of data movement and increase real time response through increased edge data analytics. This dissertation presents the design of a prototype softcore RISC-V based LoRa end node Printed Circuit Board (PCB) design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to the above. The design utilises the open source python framework LiteX to generate an open, low cost and flexible System on a Chip (SoC) that contains the necessary core and peripherals to facilitate integration with a LoRa transceiver. The SoC is implemented on an ultra low power FPGA (Lattice iCE40UP5k), providing access to both reconfigurable logic and a CPU for data analytics, and standard interfaces for 3rd party sensors, such UART, I2C and SPI. The whole design is integrated on a custom PCB in a USB dongle form factor. The resulting prototype can therefore be used as a peripheral for existing systems that may require additional compute power and IoT connectivity. The performance of the prototype is evaluated in various applicable outdoor and indoor scenarios and is observed to have comparative results with industry standard modules. |
| format | Thesis |
| id | oai:open.uct.ac.za:11427/39817 |
| institution | University of Cape Town (South Africa) |
| language | eng |
| last_indexed | 2026-06-10T12:33:49.949Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UCTD — University of Cape Town Open Access Repository |
| publishDate | 2024 |
| publishDateRange | 2024 |
| publishDateSort | 2024 |
| publisher | Department of Electrical Engineering |
| publisherStr | Department of Electrical Engineering |
| record_format | dspace |
| source_str | UCTD — University of Cape Town Open Access Repository |
| spelling | oai:open.uct.ac.za:11427/39817 Design and Implementation of a Risc-V Based LoRa Module Njoroge, Mark Winberg, Simon Engineering The proliferation of the Internet of Things(IoT) in both scale and complexity, alongside advances in optimised edge and fog system architectures, is driving an increasing need for low power end nodes with greater computational capabilities. These distributed higher capacity nodes allow IoT infrastructures to minimise the power cost of data movement and increase real time response through increased edge data analytics. This dissertation presents the design of a prototype softcore RISC-V based LoRa end node Printed Circuit Board (PCB) design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to the above. The design utilises the open source python framework LiteX to generate an open, low cost and flexible System on a Chip (SoC) that contains the necessary core and peripherals to facilitate integration with a LoRa transceiver. The SoC is implemented on an ultra low power FPGA (Lattice iCE40UP5k), providing access to both reconfigurable logic and a CPU for data analytics, and standard interfaces for 3rd party sensors, such UART, I2C and SPI. The whole design is integrated on a custom PCB in a USB dongle form factor. The resulting prototype can therefore be used as a peripheral for existing systems that may require additional compute power and IoT connectivity. The performance of the prototype is evaluated in various applicable outdoor and indoor scenarios and is observed to have comparative results with industry standard modules. 2024-05-31T12:02:32Z 2024-05-31T12:02:32Z 2023 2024-05-30T09:52:25Z Thesis / Dissertation Masters MSc http://hdl.handle.net/11427/39817 eng application/pdf Department of Electrical Engineering Faculty of Engineering and the Built Environment |
| spellingShingle | Engineering Njoroge, Mark Design and Implementation of a Risc-V Based LoRa Module |
| thesis_degree_str | Master's |
| title | Design and Implementation of a Risc-V Based LoRa Module |
| title_full | Design and Implementation of a Risc-V Based LoRa Module |
| title_fullStr | Design and Implementation of a Risc-V Based LoRa Module |
| title_full_unstemmed | Design and Implementation of a Risc-V Based LoRa Module |
| title_short | Design and Implementation of a Risc-V Based LoRa Module |
| title_sort | design and implementation of a risc v based lora module |
| topic | Engineering |
| url | http://hdl.handle.net/11427/39817 |
| work_keys_str_mv | AT njorogemark designandimplementationofariscvbasedloramodule |