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State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

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Published in:VLSI Design
Format: Online Article RSS Article
Published: 2017
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container_title VLSI Design
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discipline_display Computer Science
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genre Journal Article
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journal_source_facet VLSI Design
last_indexed 2026-06-20T21:40:03.057Z
publishDate 2017
publishDateSort 2017
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spellingShingle State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
Computer Science
General
Computer Science
sub_discipline_display General
sub_discipline_facet General
subject_display Computer Science
General
Computer Science
subject_facet Computer Science
General
Computer Science
title State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_alt Heurística de derrame consciente de transiciones de estado para registros basados en MLC STT-RAM
Heuristique de déversement consciente des transitions d'état pour les registres basés sur MLC STT-RAM
Heurística de Derramamento Ciente de Transição de Estado para Registradores Baseados em MLC STT-RAM
title_auth State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_es_txt Heurística de derrame consciente de transiciones de estado para registros basados en MLC STT-RAM
title_fr_txt Heuristique de déversement consciente des transitions d'état pour les registres basés sur MLC STT-RAM
title_full State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_fullStr State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_full_unstemmed State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_pt_txt Heurística de Derramamento Ciente de Transição de Estado para Registradores Baseados em MLC STT-RAM
title_short State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_sort state-transition-aware spilling heuristic for mlc stt-ram-based registers
topic Computer Science
General
Computer Science
url https://www.hindawi.com/journals/vlsi/2017/1030249/