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A Cache System Design for CMPs with Built-In Coherence Verification

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Published in:VLSI Design
Format: Online Article RSS Article
Published: 2016
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container_title VLSI Design
description
discipline_display Computer Science
discipline_facet Computer Science
format Online Article
RSS Article
genre Journal Article
id rss_article:78822
institution FRELIP
journal_source_facet VLSI Design
publishDate 2016
publishDateSort 2016
record_format rss_article
spellingShingle A Cache System Design for CMPs with Built-In Coherence Verification
Computer Science
General
Computer Science
sub_discipline_display General
sub_discipline_facet General
subject_display Computer Science
General
Computer Science
Computer Science
General
Computer Science
subject_facet Computer Science
General
Computer Science
title A Cache System Design for CMPs with Built-In Coherence Verification
title_auth A Cache System Design for CMPs with Built-In Coherence Verification
title_full A Cache System Design for CMPs with Built-In Coherence Verification
title_fullStr A Cache System Design for CMPs with Built-In Coherence Verification
title_full_unstemmed A Cache System Design for CMPs with Built-In Coherence Verification
title_short A Cache System Design for CMPs with Built-In Coherence Verification
title_sort a cache system design for cmps with built-in coherence verification
topic Computer Science
General
Computer Science
url https://www.hindawi.com/journals/vlsi/2016/8093614/